Minutes, IBIS Quality Committee 24 oct 2006 11-12 AM EST (8-9 AM PST) Phone: 1.877.384.0543 or 1.800.743.7560 Web access: http://meetingplace.cisco.com/join.asp?2100472 ROLL CALL Adam Tambone Barry Katz Benny Lazer Benjamin P Silva Bob Ross, Teraspeed Consulting Group Brian Arsenault * David Banas, Xilinx * Eckhard Lenski Eric Brock Gregory R Edlund Hazem Hegazy John Figueroa John Angulo Katja Koller Kevin Fisher * Kim Helliwell, LSI Logic Lance Wang Lynne Green * Mike LaBonte, Cisco * Moshiul Haque, Micron Technology Peter LaFlamme Robert Haller * Roy Leventhal, Leventhal Design & Communications Sherif Hammad Todd Westerhoff Tom Dagostino Kazuyoshi Shoji Sadahiro Nonoyama Everyone in attendance marked by * NOTE: "AR" = Action Required. -----------------------MINUTES --------------------------- Mike LaBonte conducted the meeting. AR Review: - Mike put link to http://ibis.siemens.com on IQ web Done - Mike post Moshiul's updated IQ specification to IQ web Done - David find out how Xilinx determines DC thresholds. The actual thresholds are much better than the SSTL2 requirements. Documentation is in line with SSTL standards family, however. In the process we are giving up 100s of ps of margin that could be used. Opens for new items: David asked about the requirement that package pinout must be given completely. There must be an exception for FPGA "prototype" IBIS files, which contain one of every buffer type and one pin reference to each buffer. The exact pinout for an FPGA is not known until the part design is converted to IBIS using a software tool. We reviewed the draft 1.1 IQ specification. There was some discussion about how many quality levels to have. It was clarified that additional levels would exist not to require more checks, but rather to divide the checks into a more finely grained level rating system. David asked about simulation and measurement criteria. We went over the history a little, mentioning the IBIS Accuracy Handbook as the origin. For comparison with simulation Xilinx looks at: - rise/fall time - high/low voltage levels achieved - duty cycle The final level numbering we arrived at is: - level 0 : no checking performed - level 1 : ibischk run only - level 2 : data checks to insure usefulness for basic waveform simulation - level 3 : data checks to insure usefulness for timing analysis - level 4 : data checks to insure usefulness for power/ground analysis The section that describes the levels will include lists of checks required to achieve each level. We agreed to change the specification from a simple text document to MS Word format. A table of contents will be included. AR: Mike make agreed changes to IQ spec and post as an MS Word document. Next meeting: 31 Oct 2006 11-12 AM EST (8-9 AM PST) Web access: http://meetingplace.cisco.com/join.asp?2105707 Meeting ended at 1:01 PM Eastern Time.